Embedded Solution - DDR2
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Description
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The Avexir DDR2-533/667/800 Unbuffered and SO DIMM is designed to meet the 533/667/800MHz data-rate specification of the JEDEC (Joint Electron Device Engineering Council) standard, but it seems to own the huge potentiality to draw out higher performance in Avexir laboratories. By 1.8V low-voltage application, DDR2 modules can reduce about 50% power consumption, which is compared with 2.5V (DDR) power supply on the same operation speed. So it is an environment-friendly product. In order to achieve so amazing high operation speed, AVEXIR applies the lower parasitic-loading FBGA (Fine-pitch BGA) package to run in full-speed without extraneous loading. Also, these modules are available in single and dual channel configurations.
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Specifications / Features
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- Density : 512MB / 1GB / 2GB
- Package: 240-pin dual in line memory module (U-DIMM)
- Package: 200-pin small outline dual in line memory module (SO-DIMM)
- Power supply: VDD = 1.8V +/- 0.1V
- Frequency: 533 / 667 / 800Mhz
- Interface: SSTL_18
- Burst lengths (BL): 4, 8
- /CAS Latency (CL): 3, 4, 5, 6
- Precharge: auto precharge option for each burst access
- Refresh: auto-refresh, self-refresh
- Refresh cycles: 8192 cycles/64ms
-Average refresh period
7.8 µs at 0'C <= TC <= +85'C
3.9 µs at +85'C < TC <= +95'C
- Double-data-rate architecture; two data transfers per clock cycle
- The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
- Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver
- DQS is edge-aligned with data for READs; centeraligned with data for WRITEs
- Differential clock inputs (CK and /CK)
- DLL aligns DQ and DQS transitions with CK transitions
- Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
- Data mask (DM) for write data
- Posted /CAS by programmable additive latency for better command and data bus efficiency
- Off-Chip-Driver Impedance Adjustment and On-Die-Termination for better signal quality
- /DQS can be disabled for single-ended Data Strobe operation
- Serial presence detect with EEPROM
- All of Lead-free products are compliant for RoHS
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Ordering Information
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Type |
Pin |
Capacity |
Speed |
Bandwidth |
Timing |
(Unbuffered) |
(Pin) |
(MB/GB) |
(MHz) |
(MB/s) |
CL-tRCD-tRP-tRAS |
U-DIMM |
240 |
512MB~2GB |
DDR2-533 |
PC2-4200 |
4-4-4-12 |
U-DIMM |
240 |
512MB~2GB |
DDR2-667 |
PC2-5300 |
5-5-5-15 |
U-DIMM |
240 |
512MB~2GB |
DDR2-800 |
PC2-6400 |
5-5-5-18 |
SO-DIMM |
200 |
512MB~2GB |
DDR2-533 |
PC2-4200 |
4-4-4-12 |
SO-DIMM |
200 |
512MB~2GB |
DDR2-667 |
PC2-5300 |
5-5-5-15 |
SO-DIMM |
200 |
512MB~2GB |
DDR2-800 |
PC2-6400 |
5-5-5-18 |
* All DDR2 memory modules above are
available in single and dual channel configurations |
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